In general, multiport memories refer to memory circuits which include both a random access memory (RAM) and serial access memories (SAMs). The SAMs are used to receive data input and transfer the data to the RAM. SAMs are also used to retrieve data from the RAM and output the data from the memory circuit. Multiport memories can be used as network switches. That is, the general increase in network traffic requires fast, efficient methods of managing traffic and congestion. One problem area in network traffic management occurs at line switching where a switch is used to route data from one set of communication lines to another set of communication lines. Network switches can comprise a multiport memory which is used to temporarily store a transmission during the switching operation. These switches are particularly useful in asynchronous transfer mode (ATM) communication systems.
A simplified block diagram of a multi-port memory 90 shown in FIG. 1 can be used for asynchronous transfer mode (ATM) networks. The memory has a random access memory (RAM) 92 and eight input serial access memories (SAMs) 94(0)-(7) and eight output SAMs 96(0)-(7). ATM communication packages, or cells, flow through input ports into the input SAM's. The ATM cells are transferred to the RAM and then eventually transferred to the output SAM's where the ATM cells are output on communication lines via output ports. ATM cells are a fixed length of data bits which are transmitted in an asynchronous manner. While the data length is the same for each ATM cell, the data rate of transmission can vary between networks.
Each input SAM of the multiport memory of FIG. 1 can receive one bit of an ATM cell on an input clock cycle. The input data rate of the multiport memory is therefore limited by the speed of the input clock. Memory circuit design constraints currently prohibit operating the input clocks at speeds which are needed to achieve upper limit data rates for ATM transmissions. The width of input data, therefore, must be increased to increase the data input rate. That is, by inputting data in a parallel manner, the input data rate can be increased. As such, multiport memories can be specifically designed to operate at a given input data rate. The memory circuits, however, are specifically made for a given operation and are therefore not useful in systems operating at a different data rate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an adjustable data width multiport memory circuit which can be easily configured to operated at a number of different data rates.